Supplement of Lecture 5: VHDL Codes of some Combinational Devices.

VHDL model of comparator (8 bits):

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

-- 8 Bit Unsigned Comparator

entity cmp8 is

port (

A, B: in std_logic_vector(7 downto 0);

aeqb, altb, agtb: out std_logic

);

end cmp8;

architecture a of cmp8 is

begin

aeqb < = '1' when (a = b) else '0';

altb < = '1' when (a < b) else '0';

agtb < = '1' when (a > b) else '0';

end;

The operators =, /=, < =, <, >, > = are defined in the std_logic_arith package which is part of the IEEE library.

-- vhdl model for the 3 to 8 decoder

--*************************************************************************

-- IO Interface Declaration

--*************************************************************************

library ieee;

use ieee.std_logic_1164.all;

entity dec3to8 is

port

(

-- inputs

signal sel: in std_logic_vector(2 downto 0); -- selector

signal en: in std_logic; -- enable

-- outputs

signal y: out std_logic_vector(7 downto 0) -- outputs are high true

);

end dec3to8;

--*************************************************************************

-- Architecture body

--*************************************************************************

architecture behavior of dec3to8 is

begin

process (sel, en)

begin

y < = " 11111111";

if (en = '1') then

case sel is

when " 000" => y(0) < = '1';

when " 001" => y(1) < = '1';

when " 010" => y(2) < = '1';

when " 011" => y(3) < = '1';

when " 100" => y(4) < = '1';

when " 101" => y(5) < = '1';

when " 110" => y(6) < = '1';

when " 111" => y(7) < = '1';

when others => y(7) < = '1';

end case;

end if;

end process;

end behavior;

74LS138 (3 x 8 decoder)

VHDL Code:

Library ieee

Use ieee.std_logic_1164.all;

Entity V74x138 is

Port (G1, G2A_L, G2B_L: in std_logic; -- enable inputs

A: in std_logic_vector (2 downto 0); -- select inputs A= A(2), B= A(1), C = A(0)

Y_L: out std_logic_vector (0 to 7)); -- decoded outputs

End V74x138;

Architecture V74x138_arch of V74x138 is

Signal Y_int: std_logic_vector(0 to 7);

Begin

With A select Y_int < =

“01111111” when “000”,

“10111111” when “001”,

“11011111” when “010”,

“11101111” when “011”,

“11110111” when “100”,

“11111011” when “101”,

“11111101” when “110”,

“11111110” when “111”,

“11111111” when others;

Y_L< =Y_L_i when (G1 and not G2A_L and not G2B_L) =’1’ else “11111111”;

End V74x138_arch;

-- vhdl model for 8 level priority circuit

--*************************************************************************

-- IO Interface Declaration

--*************************************************************************

library ieee;

use ieee.std_logic_1164.all;

entity priority_new is

port

(

-- inputs

signal y1: in std_logic;

signal y2: in std_logic;

signal y3: in std_logic;

signal y4: in std_logic;

signal y5: in std_logic;

signal y6: in std_logic;

signal y7: in std_logic;

-- outputs

signal vec: out std_logic_vector(2 downto 0)

);

end priority_new;

--*************************************************************************

-- Architecture body

--*************************************************************************

architecture behavior of priority_new is

begin

process (y1, y2, y3, y4, y5, y6, y7)

begin

vec < = " 000";

if (y1 = '1') then vec < = " 001";

end if;

if (y2 = '1') then vec < = " 010";

end if;

if (y3 = '1') then vec < = " 011";

end if;

if (y4 = '1') then vec < = " 100";

end if;

if (y5 = '1') then vec < = " 101";

end if;

if (y6 = '1') then vec < = " 110";

end if;

if (y7 = '1') then vec < = " 111";

end if;

end process;

end behavior;

VHDL model of a 4 to 1 multiplexers

library ieee;

use ieee.std_logic_1164.all;

-- 4 to 1 mux, 8 bit inputs, using concurrent statements

entity mux4to1_8_conc is

port (

I0, I1, I2, I3: in std_logic_vector(7 downto 0);

sel: in std_logic_vector(1 downto 0);

dout: out std_logic_vector(7 downto 0)

);

end mux4to1_8_conc;

architecture a of mux4to1_8_conc is

begin

WITH sel SELECT

dout < = I0 when " 00",

I1 when " 01",

I2 when " 10",

I3 when others;

end a;